• DocumentCode
    2516519
  • Title

    BASIC: an advanced high-performance bipolar process

  • Author

    van der Velden, J. ; Dekker, R. ; van Es, R. ; Jansen, S. ; Koolen, M. ; Kranen, P. ; Maas, H. ; Pruijmboom, A.

  • Author_Institution
    Philips Res. Lab., Eindhoven, Netherlands
  • fYear
    1989
  • fDate
    3-6 Dec. 1989
  • Firstpage
    233
  • Lastpage
    236
  • Abstract
    A novel high-performance bipolar process suitable for analog applications is described. A self-aligned technology called BASIC (best alignment with sidewall contact) yields a sidewall contacted structure with strongly reduced parasitic capacitances and low base resistance. The base link-up problem, which is of particular importance for analog applications, is eliminated in the BASIC process by the introduction of a well-defined submicron region, into which a link-up base adjustment dose can be implanted. A simple, novel polysilicon planarization method has been used to form sidewall contacted base boosts. The method is based on the controlled diffusion of boron in polysilicon, followed by the selective wet etching of undoped polysilicon. DC and AC characteristics for the npn transistor exhibit a combination of properties that makes this process very suitable for analog applications, featuring a maximum f/sub T/ of 17 GHz and an Early voltage of 80 V. Two-dimensional device simulations indicate that the increase in Early voltage by more than a factor of two for narrow emitters is caused by lateral depletion of the collector region underneath the intrinsic emitter-base region.<>
  • Keywords
    bipolar transistors; semiconductor technology; 17 GHz; 2D device simulation; 80 V; AC characteristics; BASIC; DC characteristics; Early voltage; Si:B; advanced high-performance bipolar process; analog applications; best alignment with sidewall contact; controlled diffusion; intrinsic emitter-base region; link-up base adjustment dose; low base resistance; narrow emitters; npn transistor; polycrystalline Si; polysilicon planarization method; reduced parasitic capacitances; selective wet etching; self-aligned technology; sidewall contacted base boosts; sidewall contacted structure; Anisotropic magnetoresistance; Boron; Conductivity; Fabrication; Implants; Oxidation; Planarization; Silicon; Transistors; Wet etching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
  • Conference_Location
    Washington, DC, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-0817-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1989.74268
  • Filename
    74268