DocumentCode :
2516588
Title :
Threshold voltage of sub-10-nm-thick SOI MOSFET´s at cryogenic temperature and quantum effects
Author :
Omura, Yasuhisa ; Nakakubo, Atsushi ; Nakatsuji, Hiroshi
Author_Institution :
Fac. of Eng., Kansai Univ., Osaka, Japan
fYear :
2004
fDate :
4-7 Oct. 2004
Firstpage :
53
Lastpage :
54
Abstract :
We discuss the temperature dependence of the threshold voltage of fully-depleted SOI MOSFETs with 10 nm and 6 nm thick SOI layers both theoretically and experimentally at cryogenic temperatures. The theoretical temperature dependence of VTH is derived on taking into account the effect of gate electrode degeneracy and the two-dimensional electrons with energy quantisation in the SOI layer.
Keywords :
MOSFET; cryogenic electronics; elemental semiconductors; semiconductor device models; silicon-on-insulator; 10 nm; 10-nm-thick SOI MOSFET; 6 nm; SOI layers; Si; cryogenic temperature; energy quantisation; fully-depleted SOI MOSFET; gate electrode degeneracy; quantum effects; temperature dependence; threshold voltage; two-dimensional electrons; Atmospheric measurements; Atmospheric modeling; Charge carrier processes; Cryogenics; Electrodes; Electrons; Interface states; Quantization; Temperature; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2004. Proceedings. 2004 IEEE International
Print_ISBN :
0-7803-8497-0
Type :
conf
DOI :
10.1109/SOI.2004.1391552
Filename :
1391552
Link To Document :
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