A VLSI systolic quadratic residue DFT with fault tolerance

The authors discuss the theory and construction of high-speed VLSI DFT (discrete Fourier transform) computational array. The array uses ring arithmetic isomorphic to the direct sum of a set of small quadratic residue ring computations. The array utilizes a generic systolic cell that is used for all elements in the computational process. This includes coding into the quadratic residue number system, array computation, scaling, and reconstruction. In addition to these advantages, the cell also has a built-in fault-detection system that allows fault tolerant computation of each butterfly. Typical VLSI fabrications demonstrate the unique structure and simplicity of the arrays. Example layouts in a 3- mu m double-metal CMOS process are presented.<>