Bipolar transistor design for low process-temperature 0.5 mu m Bi-CMOS

Author

Norishima, M. ; Niitsu, Y. ; Sasaki, G. ; Iwai, H. ; Maeguchi, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

237

Lastpage

240

Abstract

A low-temperature (800-850 degrees C) processes bipolar transistor design suitable for high-performance 0.5- mu m BiCMOS process is discussed. It was found that insufficient activation of arsenic in the emitter, fast base boron diffusion in the low-concentration region caused by implantation damages for the direct-ion-implanted emitter case, and insufficient arsenic diffusion from the poly-Si for the poly-Si emitter case should be considered as serious problems when the low-temperature furnace anneal is used. High-temperature RTA (rapid thermal annealing) is shown to solve those problems. Based on the impurity diffusion behaviors and related electric bipolar characteristics, the optimum conditions and structures for bipolar transistor design for the high-performance 0.5- mu m BiCMOS process are discussed.<>

Keywords

BIMOS integrated circuits; annealing; bipolar transistors; semiconductor technology; 0.5 micron; 800 to 850 C; As activation; BiCMOS process; Si:As; Si:B; bipolar transistor design; direct-ion-implanted emitter; electric bipolar characteristics; high temperature RTA; high-performance; impurity diffusion behaviors; low process-temperature; low-temperature furnace anneal; optimum conditions; rapid thermal annealing; Bipolar transistors; Boron; CMOS process; Design engineering; Furnaces; Impurities; Process design; Rapid thermal annealing; Silicon; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74269

Filename

74269