DocumentCode
2516782
Title
Simulation of high-speed single-electron memory
Author
Mizuta, H. ; Katayama, K. ; Muller, H.-O. ; Williams, D.
Author_Institution
Cavendish Lab., Hitachi Eur. Ltd., Cambridge, UK
fYear
1998
fDate
19-21 Oct. 1998
Firstpage
17
Lastpage
20
Abstract
A novel lateral single electron memory (L-SEM) architecture and its high-speed write operation were demonstrated with a write time comparable to conventional DRAMs. Excellent subthreshold characteristics of the sense MOSFET with split gates were also presented. The robustness of the L-SEM cell structure was also discussed in terms of the offset charge issue.
Keywords
Coulomb blockade; MOSFET; circuit simulation; semiconductor device models; semiconductor storage; single electron transistors; MOSFET; high-speed single-electron memory; high-speed writing; lateral single electron memory; offset charge; split gates; subthreshold characteristics; write time; Capacitance; Circuit simulation; Equivalent circuits; Europe; Laboratories; Leakage current; Lithography; Magnetic tunneling; Single electron memory; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on
Conference_Location
Osaka, Japan
Print_ISBN
0-7803-4369-7
Type
conf
DOI
10.1109/IWCE.1998.742696
Filename
742696
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