• DocumentCode
    2516801
  • Title

    Detailed investigation of geometrical factor for pseudo-MOS transistor technique

  • Author

    Komiya, K. ; Bresson, N. ; Sato, Seiki ; Cristoloveanu, S. ; Omura, Y.

  • Author_Institution
    High-Technol. Res. Center, Kansai Univ., Osaka, Japan
  • fYear
    2004
  • fDate
    4-7 Oct. 2004
  • Firstpage
    75
  • Lastpage
    76
  • Abstract
    The ψ-MOSFET technique offers a plain and quick way to characterize the SOI wafers. We derived a simple relation for the geometrical factor, as a function of probe pressure, silicon island size, and probe spacing. An empirical expression for the modified geometrical factor (fg´) is proposed. It has been demonstrated that fg´ produces a reliable extraction of the low-field carrier mobility from ID-VG curves in ψ-MOSFETs on advanced SOI substrates.
  • Keywords
    MOSFET; carrier mobility; elemental semiconductors; semiconductor device models; silicon; silicon-on-insulator; MOSFET; SOI substrates; SOI wafers; Si; empirical expression; geometrical factor; low-field carrier mobility; probe pressure; probe spacing; pseudoMOS transistor method; silicon island size; Equations; MOSFET circuits; Probes; Shape; Silicon; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2004. Proceedings. 2004 IEEE International
  • Print_ISBN
    0-7803-8497-0
  • Type

    conf

  • DOI
    10.1109/SOI.2004.1391562
  • Filename
    1391562
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2516801