Scheduling semiconductor device test operations

Author

Carmon-Freed, Tali

Author_Institution

Dept. of Ind. Eng. & Oper. Res., Xilinx Inc., San Jose, CA, USA

fYear

1996

fDate

14-16 Oct 1996

Firstpage

482

Lastpage

485

Abstract

The problem of planning and scheduling the production of test facilities to maximize throughput and minimize cost has, therefore, been gaining importance for semiconductor manufacturers. In this paper, a classification scheme for semiconductor device testing environments is presented and various testing environments are described in detail. The mathematical models describing these test environments, and software packages intended to provide scheduling solutions for semiconductor device testing are mentioned

Keywords

integrated circuit testing; production control; production engineering computing; production testing; semiconductor device testing; test facilities; classification scheme; mathematical models; planning; production; scheduling; semiconductor device test operations; semiconductor manufacture; software packages; test facilities; testing environments classification; Costs; Job shop scheduling; Mathematical model; Production planning; Semiconductor device manufacture; Semiconductor device testing; Semiconductor devices; Software testing; Test facilities; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Manufacturing Technology Symposium, 1996., Nineteenth IEEE/CPMT

Conference_Location

Austin, TX

ISSN

1089-8190

Print_ISBN

0-7803-3642-9

Type

conf

DOI

10.1109/IEMT.1996.559792

Filename

559792