DocumentCode
2516885
Title
Eutectic solder flip chip technology for chip scale package
Author
Takubo, Chiaki ; Hirano, Naohiko ; Doi, Kazuhide ; Tazawa, Hiroshi ; Hosomi, Eiichi ; Hiruta, Yoichi
Author_Institution
Semicond. Adv. Packaging Eng. Dept., Toshiba Corp., Yokohama, Japan
fYear
1996
fDate
14-16 Oct 1996
Firstpage
488
Lastpage
493
Abstract
Chip Scale Package (CSP) has been developed by applying the flip chip technology with the eutectic Sn/Pb solder bumps. The package size is only 1 mm larger than the chip size. The eutectic solder has advantages such as a good wettability to the electrodes, a strong self-alignment effect and a low melting point. So, it is quite suitable for a chip assembly onto the plastic substrate as well as the ceramic substrate. An electroplating method has been developed for the formation of the eutectic solder bumps. The barrier metals has been selected as Ti/Ni/Pd for higher barrier effect. The flip chip interconnection process has been also developed. The various kinds of the reliability of the interconnection portion were investigated using the test vehicle of the ceramic and plastic substrate. The results of the test confirmed the reliable fabrication of the CSP using the eutectic solder flip chip technology
Keywords
electroplating; eutectic alloys; flip-chip devices; lead alloys; packaging; soldering; tin alloys; CSP fabrication; Sn-Pb; Ti-Ni-Pd; barrier metal; ceramic substrate; chip scale package; electroplating; eutectic solder bump; flip chip technology; interconnection reliability; melting point; plastic substrate; self-alignment; wettability; Assembly; Ceramics; Chip scale packaging; Electrodes; Fabrication; Flip chip; Plastics; Testing; Tin; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 1996., Nineteenth IEEE/CPMT
Conference_Location
Austin, TX
ISSN
1089-8190
Print_ISBN
0-7803-3642-9
Type
conf
DOI
10.1109/IEMT.1996.559794
Filename
559794
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