DocumentCode :
2516931
Title :
Threshold voltage model of the SOI 4-gate transistor
Author :
Akarvardar, K. ; Cristoloveanu, S. ; Gentil, P.
Author_Institution :
IMEP, Grenoble, France
fYear :
2004
fDate :
4-7 Oct. 2004
Firstpage :
89
Lastpage :
90
Abstract :
The operation of the 4-gate transistor (G4-FET) is governed by the charge coupling between front, back and lateral gates. A 2D analytical relation for the fully-depleted body potential is derived. The front-interface threshold voltage is expressed as a function of the back and lateral gate voltages for all possible back interface conditions.
Keywords :
MOSFET; elemental semiconductors; semiconductor device models; silicon-on-insulator; 2D analytical relation; SOI 4-gate transistor; Si; back gates; charge coupling; front-interface threshold voltage; fully depleted body potential; lateral gate voltages; threshold voltage model; Analytical models; Body regions; Boundary conditions; Computer hacking; Differential equations; Electrons; Low voltage; Poisson equations; Threshold voltage; Virtual manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2004. Proceedings. 2004 IEEE International
Print_ISBN :
0-7803-8497-0
Type :
conf
DOI :
10.1109/SOI.2004.1391568
Filename :
1391568
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2516931
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