Title :
Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices
Author :
Bansal, Aditya ; Paul, Bipul C. ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In this paper, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated. It is shown that in scaled devices, fringing capacitance dominates the effective gate capacitance. Hence with optimum underlap the effective gate capacitance can be reduced thereby reducing the delay and power. Gate underlapping also reduces gate direct tunneling current in the off-state.
Keywords :
MOSFET; capacitance; power consumption; semiconductor device models; 16 nm; 16 nm DGMOS devices; fringing capacitance; gate capacitance; gate tunneling current; gate underlap; power consumption; Analytical models; Capacitance; Character generation; Delay; FinFETs; Leakage current; Poisson equations; Scalability; Schrodinger equation; Tunneling;
Conference_Titel :
SOI Conference, 2004. Proceedings. 2004 IEEE International
Print_ISBN :
0-7803-8497-0
DOI :
10.1109/SOI.2004.1391570
