Title :
Parallel processor system specific for Monte Carlo analysis based on ring bus architecture
Author :
Kurino, H. ; Ono, T. ; Kuroishi, N. ; Kawata, T. ; Miyakawa, N. ; Fukase, M. ; Aibara, R. ; Koyanagi, M.
Author_Institution :
Graduate Sch. of Eng., Tohoku Univ., Sendai, Japan
Abstract :
We have developed a new parallel processor system specific for the MC analysis, to dramatically reduce the calculation time. Our parallel processor system is based on ring bus architecture. The RISC micro processor chip, which contains a ring bus interface unit (RBIU), a floating point arithmetic unit (FAU) and so on, was also developed for our system. Speed up ratio compared with a single processor reached to 13.5 at 23 PEs.
Keywords :
Monte Carlo methods; floating point arithmetic; parallel architectures; semiconductor device models; MC analysis; Monte Carlo analysis; RISC micro processor chip; device simulation; floating point arithmetic unit; parallel processor system; ring bus architecture; ring bus interface unit; speed up ratio; Analytical models; Computational modeling; Design engineering; Intelligent systems; Machine intelligence; Master-slave; Monte Carlo methods; Poisson equations; System analysis and design; Systems engineering and theory;
Conference_Titel :
Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on
Conference_Location :
Osaka, Japan
Print_ISBN :
0-7803-4369-7
DOI :
10.1109/IWCE.1998.742708
