DocumentCode :
2517115
Title :
Temperature-compensated reference circuits for SOI
Author :
Terry, S.C. ; Chen, S. ; Blalock, Benjamin J. ; Jackson, J.R. ; Dufrene, B.M. ; Mojarradi, M.M.
Author_Institution :
Dept. of ECE, Tennessee Univ., Knoxville, TN, USA
fYear :
2004
fDate :
4-7 Oct. 2004
Firstpage :
112
Lastpage :
114
Abstract :
Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G4-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-μm partially depleted (PD)-SOI process.
Keywords :
CMOS integrated circuits; compensation; elemental semiconductors; insulated gate field effect transistors; reference circuits; resistors; silicon-on-insulator; 0.35 micron; 3.3 V; FET; SOI technology; Si; bulk CMOS technology; field effect transistor; four-gate transistor; partially depleted SOI process; silicon-on-insulator; standard bandgap architecture; temperature-compensated reference circuits; temperature-stable reference current; voltage reference; zero leakage p-well resistor; CMOS technology; Doping; Integrated circuit technology; Laboratories; MOSFET circuits; Photonic band gap; Propulsion; Resistors; Temperature distribution; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2004. Proceedings. 2004 IEEE International
Print_ISBN :
0-7803-8497-0
Type :
conf
DOI :
10.1109/SOI.2004.1391579
Filename :
1391579
Link To Document :
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