DocumentCode :
2517371
Title :
Width minimization of two-dimensional CMOS cells using integer programming
Author :
Gupta, Arpan ; Hayes, J.P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear :
1996
fDate :
10-14 Nov. 1996
Firstpage :
660
Lastpage :
667
Abstract :
We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Runtimes for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.
Keywords :
CMOS integrated circuits; circuit layout CAD; circuit optimisation; integer programming; linear programming; minimisation; network routing; transistor circuits; 0-1 ILP model; 2D layout style; CMOS cell width minimization; circuit preprocessing scheme; diffusion rows; experimental results; integer linear programming; optimal layouts; routing complexity; run time; transistors; two-dimensional CMOS cells; Adders; Circuits; Computer architecture; Computer science; Linear programming; Minimization; Routing; Semiconductor device modeling; Shape control; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
Type :
conf
DOI :
10.1109/ICCAD.1996.571346
Filename :
571346
Link To Document :
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