DocumentCode
2517662
Title
Experimental gate misalignment analysis on double gate SOI MOSFETs
Author
Widiez, J. ; Daugé, F. ; Vinet, M. ; Poiroux, T. ; Previtali, B. ; Mouis, M. ; Deleonibus, S.
fYear
2004
fDate
4-7 Oct. 2004
Firstpage
185
Lastpage
186
Abstract
This paper reports for the first time an experimental analysis of gate misalignment influence on DG planar nMOSFETs performance and SCE, compared to simulations. In addition, gate coupling is demonstrated to be a sensitive parameter to evaluate the real on-wafer alignment.
Keywords
MOSFET; elemental semiconductors; silicon-on-insulator; DG planar nMOSFETs; Si; double gate SOI MOSFET; gate coupling; gate misalignment analysis; on wafer alignment; planar MOSFET; Analytical models; CMOS technology; Chemicals; Dry etching; Fabrication; MOSFETs; Performance analysis; Testing; Tin; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2004. Proceedings. 2004 IEEE International
Print_ISBN
0-7803-8497-0
Type
conf
DOI
10.1109/SOI.2004.1391609
Filename
1391609
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