Title :
A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency
Author :
Biswas, Avishek ; Sinangil, Yildiz ; Chandrakasan, Anantha P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28 nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2 V to 2.4 V with a nominal input voltage of 1 V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottom-plate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1 V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 μA to 500 μA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.
Keywords :
DC-DC power convertors; MOS capacitors; charge exchange; switched capacitor networks; FDSOI integrated reconfigurable switched capacitor; bottom-plate parasitic loss reduction; charge transfer switches; current 10 muA to 500 muA; high density implementation; metal-oxide-metal capacitors; on-chip MOM capacitor; on-chip MOS capacitor; size 28 nm; step-up DC-DC converter; voltage 1 V to 2.4 V; voltage overstress; Capacitors; DC-DC power converters; Logic gates; Switches; System-on-chip; Topology; Transistors; Body biasing; FDSOI; bottom-plate parasitic capacitance; reconfigurable; step-up DC-DC converter; switched capacitor; voltage overstress limitation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2015.2416315
