DocumentCode :
2518250
Title :
3D Integration-Present and Future
Author :
Jiang, Tom ; Luo, Shijian
Author_Institution :
Micron Technol. Inc., Boise, ID, USA
fYear :
2008
fDate :
9-12 Dec. 2008
Firstpage :
373
Lastpage :
378
Abstract :
Demand for high speed, high density, small size, and multifunctional electronic devices has driven the development of 3D integration. Both die-to-die-stack and package-on-package 3D integration are in mass production. However, through silicon via (TSV) 3D integration is the future direction. Materials and processes for TSV 3D interconnection are reviewed in this paper. Those include processes for via drilling process, via liner (insulating) material, and via filling material. The materials for thin wafer support, mechanical, and electrical interconnection for TSV devices are also discussed.
Keywords :
integrated circuit interconnections; integrated circuit packaging; 3D integration; TSV 3D interconnection; die-to-die-stack 3D integration; electrical interconnection; multifunctional electronic devices; package-on-package 3D integration; thin wafer support; Bonding; Consumer electronics; Drilling; Electronics packaging; Image sensors; Mass production; Silicon; System-on-a-chip; Through-silicon vias; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2117-6
Electronic_ISBN :
978-1-4244-2118-3
Type :
conf
DOI :
10.1109/EPTC.2008.4763463
Filename :
4763463
Link To Document :
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