Title :
Low-Temperature 3D Chip-Stacking Using Compliant Bump
Author :
Watanabe, Naoya ; Mori, Takamichi ; Asano, Tanemasa
Author_Institution :
Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan
Abstract :
We demonstrate low-temperature 3D chip-stacking (number of bumps: 25,200, bump size / bump pitch: 11 ¿m / 20 ¿m, chip-stacking temperature: 30°C) using the compliant bump. Low-temperature 3D chip-stacking was carried out by mechanical caulking using compliant bump and doughnut-shaped electrode. This method is very effective in realizing 3D chip-stacking even at room temperature.
Keywords :
chip scale packaging; integrated circuit bonding; stacking; bonding; compliant bump; doughnut-shaped electrode; low-temperature 3D chip-stacking; mechanical caulking; room temperature; size 11 mum; temperature 293 K to 298 K; temperature 30 degC; Bonding; Capacitive sensors; Circuits; Contact resistance; Electrodes; Gold; Pressing; Resins; Stacking; Temperature;
Conference_Titel :
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2117-6
Electronic_ISBN :
978-1-4244-2118-3
DOI :
10.1109/EPTC.2008.4763466
