Design and Optimization of Bump Structures of Large Die Fine Pitch Copper/Low-k FCBGA and Copper Post Interconnections

This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design, metal cracks at RDL were found for the conventional SnAg bump and Cu post samples. In order to improve the bump structure design a thermo-mechanical modeling was performed to identify the effects of different design parameters and to identify the best solution to achieve reliable assembly performance. Simulation has identified few contributing factors: RDL pad thickness, dielectric thickness, UBM via size, UBM size and chip thickness. Then a series of parametric study was performed to identify the set of design points at which the finite element analysis provides the lowest stress level in RDL pad and low-k layer of the chip. Based on the results a guideline for bump configuration is proposed. To confirm the assembly performance of the optimized bump structure, the improved design has been incorporated into final test vehicle, which has a better assembly performance with no RDL pad metal crack found.