Title :
A dynamic multithreading processor
Author :
Akkary, Haitham ; Driscoll, Michael A.
Author_Institution :
Microcomput. Res. Labs., Intel Corp., USA
fDate :
30 Nov-2 Dec 1998
Abstract :
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and executed speculatively on a simultaneous multithreading pipeline. Data prediction is used to alleviate dependency constraints and enable lookahead execution of the threads. A two-level hierarchy significantly enlarges the instruction window. Efficient selective recovery from the second level instruction window takes place after a mispredicted input to a thread is corrected. The second level is slower to access but has the advantage of large storage capacity. We show several advantages of this architecture: (1) it minimizes the impact of ICache misses and branch mispredictions by fetching and dispatching instructions out-of-order, (2) it uses a novel value prediction and recovery mechanism to reduce artificial data dependencies created by the use of a stack to manage run-time storage, and (3) it improves the execution throughput of a superscalar by 15% without increasing the execution resources or cache bandwidth, and by 30% with one additional ICache fetch port. The speedup was measured on the integer SPEC95 benchmarks, without any compiler support, using a detailed performance simulator
Keywords :
multi-threading; parallel architectures; performance evaluation; ICache; SPEC95 benchmarks; data prediction; dependency constraints; dynamic multithreading processor; performance simulator; Cache storage; Dispatching; Hardware; Multithreading; Out of order; Pipelines; Resource management; Runtime; Throughput; Yarn;
Conference_Titel :
Microarchitecture, 1998. MICRO-31. Proceedings. 31st Annual ACM/IEEE International Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-8609-X
DOI :
10.1109/MICRO.1998.742784