Low K CMOS65 Ball Grid Array 40μm Pitch Wire Bonding Process Development

IC performance and cost drive interconnect dimensions to shrink to ever-smaller sizes the RC delay becomes the dominant factor to impact IC performance. The RC delay is a function of the product of the total resistance and capacitance of the whole interconnects structure. To reduce RC delay, copper interconnects were introduced to replace aluminum. At the same time, the low K material has been widely used to replace the traditional SiO₂ inter-layer dielectric. The introduction of low k material into wafer technology brings new challenges on assembly wire bonding process. As 47 μm pad pitch application begin in mass production. The industry continues to move towards ultra fine pitch wire bonding process to compete with flip chip in pin counts. Smaller features, high density and increased pin counts also demand ultra fine pitch wire bond interconnects. Ultra fine pitch with smaller ball size also cause wire bonding reliability issue. In this paper, a CMOS65 nm low k device with 40 ¿m fine pitch was designed as test vehicle in exploring the wire bond process capability on BGA package. Bonding capillary and wire bonding parameters were selected as critical factors in this study. This paper describes the key 1st bond parameter optimization on CMOS65 low K device. ASM eagle60AP wire bonder new functions (bond enhancer, F-control, table scrub) were studied.