DocumentCode
2518499
Title
The cascaded predictor: economical and adaptive branch target prediction
Author
Driesen, Karel ; Hölzle, Urs
Author_Institution
Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
fYear
1998
fDate
30 Nov-2 Dec 1998
Firstpage
249
Lastpage
258
Abstract
Two-level predictors improve branch prediction accuracy by allowing predictor tables to hold multiple predictions per branch. Unfortunately, the accuracy of such predictors is impaired by two detrimental effects. Capacity misses increase since each branch may occupy many entries, depending on the number of different path histories leading up to the branch. The working set of a given program therefore increases with history length. Similarly, cold start misses increase with history length since the predictor must first store a prediction separately for each history pattern before it can predict branches with that history. We describe a new hybrid predictor architecture, cascaded branch prediction, which can alleviate both of these effects while retaining the superior accuracy of two level predictors. Cascaded predictors dynamically classify and predict easily predicted branches using an inexpensive predictor, preventing insertion of these branches into a more powerful second stage predictor. We show that for path-based indirect branch predictors, cascaded prediction obtains prediction rates equivalent to that of two-level predictors at approximately one fourth the cost. For example, a cascaded predictor with 64+1024 entries achieves the same prediction accuracy as a 4096-entry two-level predictor. Although we have evaluated cascaded prediction only on indirect branches, we believe that it could also improve conditional branch prediction and value prediction
Keywords
computer architecture; performance evaluation; adaptive branch target prediction; cascaded branch prediction; cascaded predictor; hybrid predictor architecture; path-based indirect branch predictors; value prediction; Application software; Computer languages; Computer science; Economic forecasting; Hardware design languages; Java; Joining processes; Libraries; Program processors; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 1998. MICRO-31. Proceedings. 31st Annual ACM/IEEE International Symposium on
Conference_Location
Dallas, TX
ISSN
1072-4451
Print_ISBN
0-8186-8609-X
Type
conf
DOI
10.1109/MICRO.1998.742786
Filename
742786
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