• DocumentCode
    2518893
  • Title

    NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level

  • Author

    Jung, Myoungsoo ; Wilson, Ellis Herbert, III ; Donofrio, David ; Shalf, John ; Kandemir, Mahmut Taylan

  • Author_Institution
    Dept. of CSE, Pennsylvania State Univ., University Park, PA, USA
  • fYear
    2012
  • fDate
    16-20 April 2012
  • Firstpage
    1
  • Lastpage
    12
  • Abstract
    As NAND flash memory becomes popular in diverse areas ranging from embedded systems to high performance computing, exposing and understanding flash memory´s performance, energy consumption, and reliability becomes increasingly important. Moreover, with an increasing trend towards multiple-die, multiple-plane architectures and high speed interfaces, high performance NAND flash memory systems are expected to continue to scale. This scaling should further reduce costs and thereby widen proliferation of devices based on the technology. However, when designing NAND flash-based devices, making decisions about the optimal system configuration is non-trivial because NAND flash is sensitive to a large number of parameters, and some parameters exhibit significant latency variations. Such parameters include varying architectures such as multi-die and multi-plane, and a host of factors that affect performance, energy consumption, diverse node technology, and reliability. Unfortunately, there are no public domain tools for high-fidelity, microarchitecture level NAND flash memory simulation in existence to assist with making such decisions. Therefore, we introduce NANDFlashSim; a latency variation-aware, detailed, and highly configurable NAND flash simulation model. NANDFlashSim implements a detailed timing model for operations in sixteen state-of-the-art NAND flash operation mode combinations. In addition, NANDFlashSim models energies and reliability of NAND flash memory based on statistics. From our comprehensive experiments using NANDFlashSim, we found that 1) most read cases were unable to leverage the highly-parallel internal architecture of NAND flash regardless of the NAND flash operation mode, 2) the main source of this performance bottleneck is I/O bus activity, not NAND flash activity itself, 3) multi-level-cell NAND flash provides lower I/O bus resource contention than single-level-cell NAND flash, but the resource contention becomes a serious problem as the number o- die increases, and 4) preference to employ many dies rather than to employ many planes promises better performance in disk-friendly real workloads. The simulator can be downloaded from http://www.cse.psu.edu/~mqj5086/nfs.
  • Keywords
    NAND circuits; flash memories; I/O bus resource contention; NAND flash activity; NAND flash operation mode combination; NAND flash-based device; NANDFlashSim; configurable NAND flash simulation model; diverse node technology; embedded system; energy consumption; high performance NAND flash memory system; high performance computing; intrinsic latency variation aware NAND flash memory system modeling; microarchitecture level NAND flash memory simulation; multilevel cell NAND flash; multiple-die architecture; multiple-plane architecture; optimal system configuration; public domain tool; reliability; single level cell NAND flash; timing model; Ash; Flash memory; Memory management; Registers; Timing; Tin;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Mass Storage Systems and Technologies (MSST), 2012 IEEE 28th Symposium on
  • Conference_Location
    San Diego, CA
  • ISSN
    2160-195X
  • Print_ISBN
    978-1-4673-1745-0
  • Electronic_ISBN
    2160-195X
  • Type

    conf

  • DOI
    10.1109/MSST.2012.6232389
  • Filename
    6232389