Finite Element Analysis of Thermal Cycling Reliability of an Extra Large Thermally Enhanced Flip Chip BGA Package with Rotated Die

Since the introduction of Thermally Enhanced Flip Chip Ball Grid Array (TEFCBGA) packages, it has been one of the popular packaging options in the market for mid to high end devices in that it effectively improves both electrical and thermal performance of the product. However, to develop a robust TEFCBGA package with extra large body size of 55 mm × 55 mm is a no easy task, especially when it contains a Cu/Low-k die of 19 mm × 19 mm in size at the same time. The presence of such a large sized die not only brings about reliability issues, e.g. delamination at Inter-Layer Dielectric (ILD) interfaces, die cracking, early flip chip bump fatigue failure and excessive package warpage, but takes up most of the precious substrate real estate available, leaving little room for the neighboring passive components. To cope with this space constraint, the die is proposed to rotate by 45° with regard to the package outline, whereby a much more flexible layout of passive devices can be achieved. However, it has yet to answer whether this modified die arrangement creates more problems than it solves. This paper initially investigated the BGA and flip chip solder joint reliability of the baseline TEFCBGA package, i.e. with standard die layout, under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Global-local and multi-level sub-modeling techniques were employed for modeling of BGA solder balls and FC solder bumps respectively. Experiments were then carried out to assess the accuracy of the FEA model.