Thermal Characterization of Package-on-Package (PoP) Configuration through Modeling

PoP, Package-on-Package, becomes more and more popular in IC packaging industry because it provides a practical solution to reduce the footprint and enables separate package test before stacking them. It is widely accepted at mobile devices, especially for logic (bottom) plus memory (top) application. Meanwhile there are several technical challenges such as top to bottom package connection problem caused by warpage, fine pitch package stack issue due to bottom package mold height and worse thermal performance than that of a single stacked package. While many studies have been conducted on warpage and new type PoP for fine pitch interconnection, there is few existing study on the thermal performance of PoP. This paper investigates thermal characteristic of PoP, especially on the thermal interactions between bottom and top packages. CFD models are established to study such interactions. It is found that bottom package usually with a higher power logic die inside has great impact on the thermal budget of top package, which is usually a stacked memory package. Normal JEDEC junction to air (thetasja) or junction to board (thetasjb) thermal resistance cannot clearly describe the PoP thermal performance since the heat distribution between top and bottom package will greatly affect the results. A thermal resistance network is proposed to better represent the performance and can also give a quick estimation of junction temperature for simple calculation. The present paper then uses some fixed power of bottom and top package to evaluate different options of improving the thermal performance.