Title :
A new high-speed and low-power LSI design of SVD-MIMO-OFDM systems
Author :
Iwaizumi, Hiroki ; Yoshizawa, Shingo ; Miyanaga, Yoshikazu
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
Abstract :
In this paper, we propose a processor for singular value decomposition (SVD) and compression/decompression of feedback matrices, which is mandatory for SVD multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems. The SVD-MIMO is a transmission method, which can suppress multi-stream interference and improve communication quality by beamforming. Because of high calculation cost, any conventional SVD processors are unsuitable for real-time processing. We have employed an application specific instruction-set processor (ASIP) architecture and have realized the high-speed/low-power design and real-time processing by the parallelization of floating point units (FPUs) and arithmetic instructions specialized in complex matrix operations.
Keywords :
MIMO communication; OFDM modulation; application specific integrated circuits; floating point arithmetic; integrated circuit design; large scale integration; low-power electronics; multiplexing equipment; singular value decomposition; SVD-MIMO-OFDM systems; application specific instruction set processor; arithmetic instructions; complex matrix operation; feedback matrix compression; feedback matrix decompression; floating point unit; high speed LSI design; low power LSI design; multiple input multiple output system; orthogonal frequency division multiplexing system; real time processing; singular value decomposition; Argon; Circuit optimization; Eigenvalues and eigenfunctions; MIMO; Matrix decomposition; Power demand;
Conference_Titel :
Communications and Information Technologies (ISCIT), 2012 International Symposium on
Conference_Location :
Gold Coast, QLD
Print_ISBN :
978-1-4673-1156-4
Electronic_ISBN :
978-1-4673-1155-7
DOI :
10.1109/ISCIT.2012.6380892
