Title :
A revised low power test architecture
Author :
Wang, Gang ; Wang, Jian
Author_Institution :
Inst. of Comput. Technol., Beijing, China
Abstract :
Circuit switching activity during scan test is high and results in high average and instantaneous power consumption, which is becoming a concern for scan-based architecture. This paper presents a novel low power compression architecture for scan testing. A low power feedback MUX is added to the scan chains structure. Also, this paper maps the sequential test planning problems to a combinational circuit which can deal with arbitrary at-speed delay-test clock schemes.
Keywords :
integrated circuit testing; low-power electronics; arbitrary at-speed delay-test clock schemes; circuit switching activity; combinational circuit; low power feedback MUX; novel low power compression architecture; power consumption; revised low power test architecture; scan chain structure; scan testing; sequential test planning problems; Circuit faults; Clocks; Computer architecture; Integrated circuit modeling; Switches; Testing; Vectors; compression architecture; low power; scan test;
Conference_Titel :
Communications and Information Technologies (ISCIT), 2012 International Symposium on
Conference_Location :
Gold Coast, QLD
Print_ISBN :
978-1-4673-1156-4
Electronic_ISBN :
978-1-4673-1155-7
DOI :
10.1109/ISCIT.2012.6380894
