DocumentCode
2519452
Title
Development of Evaluation Approach for Delamination Considering Micro-Scale Interfacial Layer Structure between Resin and Silicon
Author
MATSUMOTO, Tsubasa ; Yu, Qiang ; Shibutani, Tadahiro ; MATSUZAKI, Tomio
Author_Institution
Dept. of Mech. Eng. & Mater. Sci., Yokohama Nat. Univ., Yokohama, Japan
fYear
2008
fDate
9-12 Dec. 2008
Firstpage
816
Lastpage
820
Abstract
Interconnect technology is the key to the reliability of electronic devices. Electronic components are soldered to a printed circuit board (PCB). Major failure mode is thermal fatigue of solder joints since there is a big difference in the coefficient of thermal expansion (CTE) between soldered components. Underfill resin is used to improve the interconnect reliability. Resin can relief stresses in solder joints due to the mismatch in CTE. On the other side, resin creates another reliability concern to interfacial failures of metal/resin and ceramic/resin. Interfacial failure has been often evaluated as the fracture toughness based on fracture mechanics, where the interface is assumed as the boundary of components and has a perfect bonding. Then, the stress intensity factor is a key parameter to evaluate the interfacial strength. However, in the case of electronic devices, since there are a lot of new materials and since new combination of materials has a different interfacial strength another methodology of estimating the interfacial strength is being required. Actually, the interface such as resin/ceramics has an imperfect bonding and consists of small structures. In this study, an alternative approach for evaluating the interfacial strength of resin in electronic components was proposed. Based on the scanning electron microscopy (SEM) observation, finite element models were constructed. The models consist of two components and interfacial layer. Parametric FEA study revealed that stresses are affected by small structures of the interface layer. It means that small structure should be considered to estimate an interfacial strength. Experiments were carried out to verify the proposed approach. 3-point bending test was performed for a specimen consisting of a silicon chip, an epoxy resin and a FR-4 substrate. Delamination load was measured as interfacial strength. FEA of the 3-point bending test was also performed to estimate the critical load for delamination. Prop- osed approach agrees with experimental results.
Keywords
finite element analysis; printed circuits; reliability; scanning electron microscopy; silicon; solders; 3-point bending test; FR-4 substrate; Si; ceramic/resin; delamination; evaluation approach; fracture mechanics; fracture toughness; interconnect technology; interfacial strength; metal/resin; micro-scale interfacial layer structure; printed circuit board; reliability; resin; scanning electron microscopy; silicon; solder joints; stress intensity factor; thermal expansion; thermal fatigue; Bonding; Ceramics; Delamination; Electronic components; Integrated circuit interconnections; Resins; Silicon; Soldering; Stress; Thermal expansion;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location
Singapore
Print_ISBN
978-1-4244-2117-6
Electronic_ISBN
978-1-4244-2118-3
Type
conf
DOI
10.1109/EPTC.2008.4763532
Filename
4763532
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