A pipelined charge-balancing A/D converter

To improve sampling rate of a charge-balancing analog-to-digital (A/D) converter, a pipelined architecture is proposed. The new A/D converter is based on cyclic charge-balancing A/D conversion, which improves the conversion speed of the charge-balancing A/D converter implemented by a switched capacitor. A prototype of the pipelined charge-balancing A/D converter was implemented using several switched-capacitor blocks, each of which was composed of discrete circuit components. Due to the concurrent operations of each block, a high throughput rate was realized. The linearity error of the prototype is estimated as less than ±0.5 (LSB) at a 9-b resolution. The implementation of the bipolar conversion by using one reference voltage is confirmed as an effective design