Process variation verification of low-power secure CSSAL AES S-box circuit

Author

Monteiro, Carlos ; Takahashi, Y. ; Sekine, Taku

Author_Institution

Grad. Sch. of Eng., Gifu Univ., Gifu, Japan

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

21

Lastpage

24

Abstract

In this work, we implement our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using a multi-stage positive polarity Reed-Muller (PPRM) representation with a composite field technique. We evaluate the effectiveness of the CSSAL S-box circuit against side-channel attacks towards the variations of the CMOS process technology. The results of this paper are obtained from the SPICE simulation with 0.18-μm and 90-nm standard CMOS technology at an operating frequency band of 125 KHz-70 MHz.

Keywords

CMOS logic circuits; cryptography; low-power electronics; CMOS process technology; PPRM representation; S-box circuit; SPICE simulation; charge-sharing symmetric adiabatic logic; composite field technique; frequency 125 kHz to 70 MHz; low-power secure CSSAL AES S-box circuit; multistage positive polarity Reed-Muller representation; process variation verification; side-channel attacks; size 0.18 mum; size 90 nm; word length 8 bit; CMOS integrated circuits; CMOS process; Cryptography; Integrated circuit modeling; Semiconductor device modeling; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908342

Filename

6908342