Chip In Wafer for Integrated System

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new system in package (SiP) architectures, which combine a whole range of different technologies. However, cost is the critical issue in SiP packaging as individual operations are currently necessary to complete each individual package. Taking into account all the developments that have been made to date on wafer level packaging, it has been proposed to establish SiP at wafer level. The process presented in this paper proposes to use silicon wafer as frame. Known Good Dies are fitted into through cavities and sealed with polymer. This process enables coplanar chip active face with the host silicon wafer. Due to the consistency given by the silicon frame, the wafer can be treated in wafer line for the above IC process such as passive integration, via plating and pad redistribution, bumping, testing and dicing. The paper describes technologies developed for chip integration in silicon wafer (CIW) and first results on wafer characterization will be set out.