• DocumentCode
    2520021
  • Title

    Package Design Optimization for Electrical Performance of a Power Module using Finite Element Analysis

  • Author

    Erwin, I.V.A. ; Paek, Seung-Han ; Lee, Taek-Keun

  • Author_Institution
    Adv. Package Technol. Group, Fairchild Semicond., Cebu, Philippines
  • fYear
    2008
  • fDate
    9-12 Dec. 2008
  • Firstpage
    1023
  • Lastpage
    1027
  • Abstract
    This paper presents the development of a high power module package having improved its electrical performance optimizing the package structure and the circuit layout on a substrate throughout Finite Element Analysis (FEA). The result of FEA shows that the modeling is finely calibrated from the verification, that is, comparing it with actual measurement values of several types of design configuration. This module package is used for synchronous rectification and contains MOSFETs, resistors and a driver IC. High electrical current over as much as 100A should flow through the devices, interconnect materials, traces and the Cu leads of the package. In order to decrease the on-state resistance or RDS(ON), the package design needs to be investigated to find ways of improving the high electrical resistance paths such as the interconnect wires and traces. The authors initially worked on a simple 3D Finite Element Model using a commercial Finite Element Analysis (FEA) software ANSYS® and correlated the results with an actual experiment. After establishing the model, a variety of bonding configurations of Aluminum wire bonding and Cu clip bonding are investigated to achieve the optimum RDS(ON), and modifying the design of the leadframe is also studied. Aside from improving the electrical resistance, it is also necessary that the circuit will have a comparable RDS(ON) value so that the thermal effects of the individual devices would be similar.
  • Keywords
    MOSFET; driver circuits; electrical resistivity; finite element analysis; integrated circuit interconnections; integrated circuit layout; integrated circuit packaging; lead bonding; modules; resistors; ANSYS; FEA; MOSFETs; circuit layout; clip bonding; driver IC; finite element analysis; high power module package; interconnect materials; leadframe-on-substrate assembly; on-state resistance; resistors; synchronous rectification; thick die attach paddle; wire bonding; Bonding; Design optimization; Electric resistance; Finite element methods; Integrated circuit interconnections; Integrated circuit packaging; MOSFETs; Multichip modules; Performance analysis; Resistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-2117-6
  • Electronic_ISBN
    978-1-4244-2118-3
  • Type

    conf

  • DOI
    10.1109/EPTC.2008.4763564
  • Filename
    4763564