Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure

In this paper we develop a general model based on the width of a decoupling NMOS gate capacitor for use in the design of decoupling based Power Analysis Attack (PAA) countermeasures. A polynomial equation was determined based on experimental data to link the width of the decoupling element with the data security provided by the countermeasure architecture. The proposed model is meant to act as a tool for a designer when considering the incurred design overheads when allocating area during the initial planning phase. Experimental data was collected from the simulation of a partial decoupling countermeasure test bench implemented in 65 nm TSMC technology with Correlation Power Analysis (CPA) attacks performed on traces collected at the power supply pin.