Detailed analysis of implementation options for timed finite state machines in hardware

Very few topics affect a larger audience of digital circuit designers than the subject of correctly designing and implementing finite state machines (FSMs) in hardware. For that purpose, it was shown recently that any FSM can be classified into one of just three categories, called regular, timed, and recursive FSMs. The main problem, highly subject to gross errors in practice and not properly covered by any EDA tool, is the implementation of the timed machines, because the timer must be simple and, more importantly, it is the FSM itself who must control the timer, deciding when (and how) it should run, stop, or be zeroed. This paper addresses this issue by presenting a detailed analysis of two timer-control strategies, along with corresponding circuits, design variations, pros and cons, and experimental results with hardware and power consumption measurements from implementations in three FPGA devices.