An improvement technique for the test compression ratio and application time of multiple expansion scan chain based SoC using new cost function

The importance of an efficient methodology for testing defects generated during IC manufacturing process is more than ever significant as the complexity of system on a chip (SoC) increases. Scan test is the most prevalent method for detecting stuck-at faults of digital integrated circuits. There are great demands for more efficient and lossless improvement techniques to reduce test cost growth caused by increase in chip density. In this paper, we propose a new multiple expansion scan chain (MESC) based technique by exploiting novel cost function considering additional variables for the total chain length of concatenated chains and sophisticated dependency analysis between each pair of chains. This proposed method is applied to two digital IP blocks of state-of-the-art mobile SoC fabricated in 14nm CMOS process. Experimental results show that the test data volume (TDV) is reduced by 10.4% and the longest chain length (LCL) decreases by 47.1% in maximum respectively when compared to existing works.