• DocumentCode
    2520521
  • Title

    In the development and evaluation of specialized processors for computing high-order 2-D image moments in real-time

  • Author

    Roma, Nuno ; Sousa, Leonel

  • Author_Institution
    Dept. of Electr. Eng., Inst. Superior Tecnico, Lisbon, Portugal
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    170
  • Lastpage
    179
  • Abstract
    Image moments are used in image analysis for object modelling, matching and representation. The computation of high-order moments is a computational intensive task that can not be implemented in real-time with nowadays general-purpose processors. This paper proposes a set of specialised processors for generating an image moment of an arbitrary order in real time, by adopting systolic processing techniques and floating-point arithmetic units. It proposes a modular and cost effective architecture for generating image moments, with a processing time not dependent on the order of the computed moments. The architecture was implemented using different devices, such as programmable digital processors, configurable hardware logic and integrated circuits, by using a 0.7 μm CMOS process. The several implementations have shown the effectiveness of the architecture, and the obtained results allow us to compare the different solutions in terms of speed, flexibility, cost and power consumption
  • Keywords
    digital signal processing chips; floating point arithmetic; object recognition; real-time systems; systolic arrays; computational intensive task; configurable hardware logic; floating-point arithmetic; high-order 2-D image moments; image analysis; object matching; object modelling; programmable digital processors; real-time system; specialized processors; systolic processing; CMOS digital integrated circuits; CMOS integrated circuits; CMOS logic circuits; Computer architecture; Costs; Floating-point arithmetic; Hardware; Image analysis; Image generation; Logic devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architectures for Machine Perception, 2000. Proceedings. Fifth IEEE International Workshop on
  • Conference_Location
    Padova
  • Print_ISBN
    0-7695-0740-9
  • Type

    conf

  • DOI
    10.1109/CAMP.2000.875975
  • Filename
    875975