Title :
Extracting functional modules from flattened gate-level netlist
Author :
Shi, Yiqiong ; Gwee, Bah-Hwee ; Ren, Ye ; Phone, Thet Khaing ; Ting, Chan Wai
Author_Institution :
Integrated Syst. Res. Lab., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
A generic and highly versatile method for extracting functional modules from a flattened gate-level netlist is proposed. The proposed method requires no prior knowledge about the netlist under analysis and is applicable to circuits targeting diverse applications. It is fully automated and employs a highly compact module library containing only single generic model for each common function type with arbitrary data width. Experiment results depict the efficacy of the proposed method and its embodied techniques.
Keywords :
logic circuits; logic gates; logic testing; arbitrary data width; circuit analysis; compact module library; flattened gate-level netlist; functional module extraction method; signature testing; single generic model; subcircuit cross matching test; Cascading style sheets; Data structures; Libraries; Logic gates; Multiplexing; Registers; Runtime; Verification; semantic equivalence checking; subcircuit recognition;
Conference_Titel :
Communications and Information Technologies (ISCIT), 2012 International Symposium on
Conference_Location :
Gold Coast, QLD
Print_ISBN :
978-1-4673-1156-4
Electronic_ISBN :
978-1-4673-1155-7
DOI :
10.1109/ISCIT.2012.6380958