Compiling and optimizing image processing algorithms for FPGAs

Author

Draper, Bruce ; Najjar, Walid ; Böhm, Wim ; Hammes, Jeff ; Rinker, Bob ; Ross, Charlie ; Chawathe, Monica ; Bins, José

Author_Institution

Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA

fYear

2000

fDate

2000

Firstpage

222

Lastpage

231

Abstract

This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some well-known image processing routines, written in SAC and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs

Keywords

data flow graphs; field programmable gate arrays; hardware description languages; image processing; optimising compilers; Annapolis Microsystems WildForce board; FPGAs; SA-C; SA-C algorithms; VHDL; Xilinx 4036XL FPGAs; data flow graphs; high-level language; image processing algorithms; image processing routines; language features; optimizing compiler; performance numbers; Acceleration; Circuit synthesis; Coprocessors; Field programmable gate arrays; Flow graphs; High level languages; Image processing; Optimizing compilers; Programmable logic arrays; Programming profession;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architectures for Machine Perception, 2000. Proceedings. Fifth IEEE International Workshop on

Conference_Location

Padova

Print_ISBN

0-7695-0740-9

Type

conf

DOI

10.1109/CAMP.2000.875981

Filename

875981