DocumentCode :
2520655
Title :
Evaluation of a Hardware-Software Codesign Technique of Network Protocol Stacks
Author :
Kim, Taehoon ; Tak, Sungwoo
Author_Institution :
Sch. of Comput. Sci. & Eng., Pusan Nat. Univ., Pusan, South Korea
fYear :
2010
fDate :
15-17 July 2010
Firstpage :
265
Lastpage :
268
Abstract :
Many studies in SoC (System-on-Chip) areas ignore the scheduling of messages exchanged between hardware-software components as a fine level of inter-component communication granularity. Such a message scheduling scheme in hardware-software codesign of SoC systems has received comparatively less attention in the literature despite their importance as an element of a complete partitioning solution. In this paper, we attempt to resolve a message scheduling problem to meet the semantics of inter-component communications. Additionally, we evaluate the performance of hardware-software codesign for network protocol stacks.
Keywords :
hardware-software codesign; processor scheduling; protocols; system-on-chip; SoC; hardware-software codesign technique; hardware-software components; inter-component communication granularity; message scheduling; network protocol stacks; performance evaluation; Hardware; Hardware design languages; Protocols; Real time systems; Software; System-on-a-chip; Time factors; Message Scheduling; Network Protocol; System-On-Chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Network Computing and Applications (NCA), 2010 9th IEEE International Symposium on
Conference_Location :
Cambridge, MA
Print_ISBN :
978-1-4244-7628-2
Type :
conf
DOI :
10.1109/NCA.2010.49
Filename :
5598195
Link To Document :
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