Title :
Loop regularization for image and video processing on instruction level parallel architectures
Author :
Zingirian, N. ; Maresca, M.
Author_Institution :
Dipt. di Elettronica e Inf., Padova Univ., Italy
Abstract :
This paper presents a novel loop transformation (Loop Regularization, LR) that increases the execution efficiency of image and video processing programs running on instruction level parallel (ILP) processors. LR is specifically, devised for those ILP processors that do not include hardware mechanisms for instruction reordering and register renaming such as today´s low cost processors for embedded systems and digital signal processors. This paper shows the effects of LR and reports on a set of system-level experiments that validate the technique
Keywords :
digital signal processing chips; embedded systems; image processing; parallel architectures; digital signal processors; embedded systems; image processing; instruction level parallel architectures; instruction reordering; loop regularization; register renaming; video processing; Application software; Computer aided instruction; Concurrent computing; Convolution; Costs; Hardware; Microprocessors; Parallel architectures; Parallel processing; Registers;
Conference_Titel :
Computer Architectures for Machine Perception, 2000. Proceedings. Fifth IEEE International Workshop on
Conference_Location :
Padova
Print_ISBN :
0-7695-0740-9
DOI :
10.1109/CAMP.2000.875985
