Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD

Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-V_DD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal V_DDL using overall optimization method that does not fully exploit the flexibility of architecture. In this paper, we adopt variable optimal V_DDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal V_DDL. Experiment shows our proposed heuristic approach could reduce the power by 19.5% on average for the loops of GPS, MPEG2, H.264 and audio video coding standard (AVS) without decreasing performance. The additional compilation time is negligible. The area penalty of this method is less than 3%.