Title :
New Approach for Wafer Level Crystal Unit Package
Author :
Kim, Tae Hoon ; Jeon, Jong Yeol ; Kwak, Yun Pyo ; Hong, Ju Pyo ; Kim, Tae Ho ; Lim, Eun Jung ; Park, Jang Ho ; Choi, Seog Moon ; Yi, Sung
Author_Institution :
Samsung Electro-Mech. Co. Ltd., Suwon, South Korea
Abstract :
The new packaging approach for crystal resonator with quartz crystal is described in this paper. We designed and optimized the structure of wafer level crystal unit package for low cost and high performance with 2.0Ã1.6Ã0.45 mm3 size. The crystal unit package is reduced in size and thickness by using a 4" wafer level package technique of general semiconductor process. Traditionally, the package substrate of crystal unit device used ceramics order\´s HTCC (high temperature co-fired ceramic) and metal lid. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The AuSn eutectic bonding between glass package wafer and Si cap wafer that is etched using DRIE (deep reactive ion etch) process protects the quartz blank mechanically and encapsulates high vacuum state. The frequency and impedance performance of wafer level crystal unit in comparison with conventional crystal unit devices is characterized.
Keywords :
ceramics; crystal resonators; electroplating; encapsulation; integrated circuit interconnections; mechanical strength; quartz; wafer bonding; wafer level packaging; cap wafer; crystal resonator; deep reactive ion etching; electro-plating; encapsulation; eutectic bonding; glass package wafer; high temperature co-fired ceramic; impedance; interconnection; mechanical strength; metal lid; quartz crystal; sand blasting; thermal strength; wafer level crystal unit package; Ceramics; Cost function; Design optimization; Etching; Glass; Mass production; Semiconductor device packaging; Substrates; Temperature; Wafer scale integration;
Conference_Titel :
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2117-6
Electronic_ISBN :
978-1-4244-2118-3
DOI :
10.1109/EPTC.2008.4763601