Design and analysis of low-voltage silicon-controlled rectifier ESD protection circuit

Author

Zitao Shi ; Jian Liu ; Xin Wang ; Lin Lin ; Wang, Xin ; Cheng, Yuhua ; Yang, Li-wu

Author_Institution

Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA

fYear

2010

fDate

15-17 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

This paper reports design and analysis of new low triggering voltage dual-polarity silicon-controlled rectifier (SCR) ESD protection structures and circuits in CMOS. Design optimization technique enables flexible ESD triggering voltage (V_t1), ESD holding voltage (V_h) and ESD protection capability. Measurements show very low and adjustable V_t1, low leakage (I_leak), low noise figure (NF), low ESD-induced parasitic capacitance (C_ESD) and fast ESD triggering time (t₁). It achieves high ESD protection to Si ratio of ESDV~6.83V/ μm².

Keywords

CMOS integrated circuits; electrostatic discharge; optimisation; thyristors; CMOS; NF; SCR; low noise figure; low-voltage silicon-controlled rectifier ESD protection circuit; optimization technique; triggering time; triggering voltage; Electrostatic discharge; Ions; Logic gates; Noise measurement; Adjustable triggering; Dual-polarity; ESD protection; RF; SCR;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-9997-7

Type

conf

DOI

10.1109/EDSSC.2010.5713722

Filename

5713722