A multichannel corticospinal interface IC for intracortical spike recording and distinct muscle pattern activation via intraspinal microstimulation

This paper reports on a corticospinal interface IC as a core building block for next-generation integrated neural interfaces targeted at functional recovery from spinal cord injury (SCI). Fabricated in 0.35μm 2P/4M CMOS, the IC integrates a 2-channel, 10b, neural-recording front-end with digitally programmable gain and bandwidth featuring total input noise voltage of 3μV_rms and noise efficiency factor (NEF) of 2.47, and a 4-channel, constant-current, stimulating back-end for delivering programmable trains of charge-balanced monophasic or asymmetric biphasic current pulses up to ~100μA. The IC functionality is demonstrated in vivo by low-noise recording of extracellular neural spikes from an anesthetized rat´s cerebral cortex, and by distinct muscle pattern activation in the rat´s hindlimb facilitated via intraspinal microstimulation (ISMS).