A clock and data recovery circuit for 3.125Gb/s RapidIO SerDes

This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to lessen the problems in routing high speed clocks and reduce power. An improved half rate bang-bang phase detector is presented to assure the stability of the system. Moreover, the paper proposes a simplified control scheme for the phase interpolator to further reduce power and cost. The CDR takes an area of less than 0.05 m m², and post simulation shows that the CDR has a RMS jitter of UI_pp/32 (11.4 ps @3.125GBaud) and consumes 9.5 mW at 3.125 GBaud.