DocumentCode
2521037
Title
Testability properties of vertex precedent BDDs
Author
Reis, André ; Prado, Alex ; Lubaszewski, Marcelo
Author_Institution
Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
fYear
2000
fDate
2000
Firstpage
15
Lastpage
20
Abstract
This paper describes how technology mapping from VPBDDs is testability preserving. An algorithm for identifying unreachable arcs is presented. Theorems that prove the testability preservation during technology mapping are presented
Keywords
binary decision diagrams; design for testability; fault diagnosis; logic design; technology mapping; testability preservation; testability properties; unreachable arcs identification algorithm; vertex precedent BDDs; Binary decision diagrams; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Data structures; Fault diagnosis; Logic circuits; Logic testing; Tail;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on
Conference_Location
Manaus
Print_ISBN
0-7695-0843-X
Type
conf
DOI
10.1109/SBCCI.2000.876002
Filename
876002
Link To Document