DocumentCode :
2521115
Title :
Enabling in-Line Flip Chip Process - A Novel Interconnect Technique of Flipchip Discrete Packaging
Author :
Livelo, Emmanuel ; Guillermo, Michelle Lyn
fYear :
2008
fDate :
9-12 Dec. 2008
Firstpage :
1340
Lastpage :
1346
Abstract :
Flip Chip packaging provides designers a competitive advantage to convert existing wired packages to smaller footprint packaging plus the overall reduction of package resistance for faster switching applications. Several interconnection techniques are available to attach a Flip Chip die to the lead frame or substrate. One of these known techniques is using a bumped die (electroplated or Cu bumped) and soldering the Flip Chip component to the lead frame via a solder paste interconnect material. Several Flip Chip equipments are available in the market offering in-line Flip Chip process solution from dispensing, Flip Chip and reflow process. In a Flip Chip process, solder paste material is deposited to the lead frame pad via dispensing process. There are several dispensing technologies capable for consistent solder dot sizes. But the use a high speed dispensing process paired with a showerhead (multi hole) dispense tool design remains a challenge to achieve faster throughput. In this study, a pneumatic dispense system and an Auger dispense system was evaluated and compared. Pneumatic dispense systems uses pressure and time parameter to dispense a solder pattern while the auger type volumetric system dispenses a solder patterns through a screw fitted in the dispense system. Both systems have advantages and disadvantages as well which needs careful characterization to prevent solder clogging in the dispense tool opening. The selection of suitable solder material characterization will also affect the overall dispensing quality.
Keywords :
chip scale packaging; flip-chip devices; integrated circuit interconnections; reflow soldering; bumped die; flip chip packaging; footprint packaging; interconnection; package resistance; reflow process; soldering; Conducting materials; Flip chip; Lead; Ovens; Packaging machines; Process control; Semiconductor device packaging; Thermal conductivity; Thermal management; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2117-6
Electronic_ISBN :
978-1-4244-2118-3
Type :
conf
DOI :
10.1109/EPTC.2008.4763617
Filename :
4763617
Link To Document :
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