A CAD tool for design and analysis of CNFET circuits

Author

Huang, Jiale ; Zhu, Minhao ; Gupta, Puneet ; Yang, Shengqi ; Rubin, Samuel M. ; Garret, Gilda ; He, Jin

Author_Institution

Sch. of Comm. & Info. Eng., Shanghai Univ., Shanghai, China

fYear

2010

fDate

15-17 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a graphical computer-aided design (CAD) environment for the design, analysis, and layout of carbon nanotube (CNT) field-effect transistor (CNFET) circuits. This work is motivated by the fact that such a tool currently does not exist in the public domain for researchers. Our tool has been integrated within Electric - a very powerful, yet free CAD system for custom design of integrated circuits (ICs). The tool supports CNFET schematic and layout entry, rule checking, and HSpice/VerilogA netlist generation. We provide users with a customizable CNFET technology library with the ability to specify λ-based design rules. We showcase the capabilities of our tool by demonstrating the design of a CNFET standard cell library and a 16-bit carry-select adder. We hope that the availability of this tool will invigorate the CAD community to explore novel ideas in CNFET circuit design.

Keywords

adders; carbon nanotubes; field effect transistors; nanotube devices; technology CAD (electronics); CNFET circuits; CNFET standard cell library; HSpice; VerilogA netlist generation; carbon nanotube field-effect transistor; carry-select adder; graphical computer-aided design; layout entry; rule checking; Adders; CNTFETs; Design automation; Hardware design languages; Layout; Libraries; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-9997-7

Type

conf

DOI

10.1109/EDSSC.2010.5713735

Filename

5713735