DocumentCode
2521229
Title
An adaptive edge enhancement algorithm and hardware implementation
Author
Long, Linkai ; Cui, Xiaoxin ; Yu, Dunshan
Author_Institution
Inst. of Microelectron., Peking Univ., Beijing, China
fYear
2010
fDate
15-17 Dec. 2010
Firstpage
1
Lastpage
3
Abstract
In this paper, a novel adaptive edge enhancement algorithm is proposed. A noise reduction algorithm operated in 5×5 block on Y channel is also presented. With the parallel and pipelined structure, the processing time for a single pixel and an image is reduced efficiently. The hardware demo is designed and verified with Xilinx Virtex2 FPGA at frequency 90 MHz.
Keywords
adaptive filters; edge detection; field programmable gate arrays; image denoising; image enhancement; Xilinx Virtex2 FPGA; Y channel; adaptive edge enhancement algorithm; frequency 90 MHz; hardware implementation; pixel; Colored noise; Frequency modulation; Image color analysis; Image edge detection; Table lookup; Variable speed drives; adaptive filter; edge enhancement; hardware implementation; noise reduction; parallelism;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location
Hong Kong
Print_ISBN
978-1-4244-9997-7
Type
conf
DOI
10.1109/EDSSC.2010.5713737
Filename
5713737
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