Title :
Core Excitation Modeling Methodology for Efficient Power Delivery Analysis
Author :
Tan, Fern Nee ; Pang, Sze Geat ; Sasidaran, Dhinesh ; Lee, Chee Siong ; Lim, Jin Sean ; Ooi, Poey Ling ; Yong, Lee Kee
Author_Institution :
Penang Design Center, Intel Microelectron. Sdn Bhd, Penang, Malaysia
Abstract :
This paper presents a comprehensive core power delivery excitation modeling approach, covering from complex pre-silicon hand estimate to simple post-silicon reverse engineering. Blending the two approaches, an optimized method is recommended to provide the most appropriate method in deriving the next generation core currents for power delivery analysis.
Keywords :
SPICE; SRAM chips; clocks; equivalent circuits; flip-flops; leakage currents; logic circuits; reverse engineering; ROM; SRAM; Spice model; cache; clock tree; core excitation modeling methodology; data lines; embedded blocks; equivalent circuit; flip-flops; leakage current; logic cells; memory blocks; next generation core currents; power delivery analysis; reverse engineering; Costs; Logic; Optimization methods; Packaging; Power engineering and energy; Reverse engineering; Robustness; Silicon; Switches; Voltage;
Conference_Titel :
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2117-6
Electronic_ISBN :
978-1-4244-2118-3
DOI :
10.1109/EPTC.2008.4763629
