Title :
Modular exponentiation on fine-grained FPGA
Author :
Tiountchik, Alexander ; Trichina, Elena
Author_Institution :
Inst. of Math., Acad. of Sci., Minsk, Byelorussia
Abstract :
Taking as a starting point for an FPGA program an efficient bit-level systolic algorithm facilitates the design process but does not automatically guarantee the most efficient hardware solution. We use an example of modular exponentiation with Montgomery multiplication to demonstrate a role of layout optimisation and partitioning in mapping linear systolic arrays onto two-dimensional arrays of FPGA cells
Keywords :
digital arithmetic; field programmable gate arrays; parallel algorithms; systolic arrays; Montgomery multiplication; bit-level systolic algorithm; fine-grained FPGA; layout optimisation; linear systolic arrays; modular exponentiation; most efficient hardware solution; partitioning; two-dimensional arrays; Algorithm design and analysis; Application software; Computer science; Field programmable gate arrays; Hardware; Mathematics; Partitioning algorithms; Process design; Programmable logic arrays; Systolic arrays;
Conference_Titel :
Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on
Conference_Location :
Manaus
Print_ISBN :
0-7695-0843-X
DOI :
10.1109/SBCCI.2000.876021
